US 12,302,573 B2
Three-dimensional memory device with backside interconnect structures
Kun Zhang, Wuhan (CN); Zhong Zhang, Wuhan (CN); Lei Liu, Wuhan (CN); Wenxi Zhou, Wuhan (CN); and Zhiliang Xia, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jun. 18, 2024, as Appl. No. 18/746,944.
Application 18/746,944 is a continuation of application No. 17/020,383, filed on Sep. 14, 2020, granted, now 12,082,411.
Application 17/020,383 is a continuation of application No. PCT/CN2020/100567, filed on Jul. 7, 2020.
Claims priority of application No. PCT/CN2020/084600 (WO), filed on Apr. 14, 2020; and application No. PCT/CN2020/084603 (WO), filed on Apr. 14, 2020.
Prior Publication US 2024/0341096 A1, Oct. 10, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer;
channel structures extending vertically through the memory stack and into the second semiconductor layer;
source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and
a backside interconnect layer over the second side of the second semiconductor layer and comprising interlayer dielectric (ILD) layers and a source line mesh on the ILD layers, wherein the source contacts are distributed on a side of the source line mesh, and the source contacts extend through the ILD layers and into the second semiconductor layer.