US 12,302,572 B2
Semiconductor memory device
So Hyeon Lee, Suwon-si (KR); Sung Su Moon, Hwaseong-si (KR); Jae Duk Lee, Seongnam-si (KR); and Ik-Hyung Joo, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO, LTD., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 5, 2023, as Appl. No. 18/530,049.
Application 18/530,049 is a continuation of application No. 17/158,494, filed on Jan. 26, 2021, granted, now 11,877,450.
Claims priority of application No. 10-2020-0084741 (KR), filed on Jul. 9, 2020.
Prior Publication US 2024/0107770 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first stacked structure on a substrate, the first stacked structure including first electrode pads stacked in a first direction and having a stair shape;
a second stacked structure on the first stacked structure, the second stacked structure including second electrode pads stacked in the first direction and having a stair shape, the second electrode pads overlapping the first electrode pads in the first direction;
a cutting line penetrating the first stacked structure and the second stacked structure; and
a first contact plug and a second contact plug penetrating the first stacked structure and the second stacked structure,
wherein one of the first electrode pads is electrically connected to the first contact plug, and one of the second electrode pads is electrically connected to the second contact plug.