US 12,302,568 B2
Semiconductor memory device including a discharge contact
Kwang Hwi Park, Icheon-si (KR); Sang Hyun Sung, Icheon-si (KR); and Sung Lae Oh, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 14, 2022, as Appl. No. 17/721,226.
Claims priority of application No. 10-2021-0171059 (KR), filed on Dec. 2, 2021.
Prior Publication US 2023/0180474 A1, Jun. 8, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 23/60 (2006.01); H10B 41/27 (2023.01); H10B 43/40 (2023.01); H10B 43/10 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/60 (2013.01); H10B 41/27 (2023.02); H10B 43/40 (2023.02); H10B 43/10 (2023.02); H10B 43/50 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory structure including a plurality of memory cells that are disposed on a cell region of a source plate;
a plurality of contact plugs passing through the source plate in a coupling region of the source plate including at least a portion of a center portion of the source plate, and separated from the source plate by a dielectric layer pattern;
a discharge contact passing through the source plate in the coupling region;
a discharge region coupled to the discharge contact, and disposed in a substrate below the source plate; and
an additional discharge contact passing through the source plate at the center portion of the source plate, intersecting with the discharge contact, and coupled to the discharge contact and the center portion of the source plate.