US 12,302,564 B2
Memory device comprising second memory cell having first terminal coupled to first signal line through first memory cell
Meng-Han Lin, Hsinchu (TW); Chia-En Huang, Hsinchu County (TW); Han-Jong Chia, Hsinchu (TW); Yi-Ching Liu, Hsinchu (TW); Sheng-Chen Wang, Hsinchu (TW); Feng-Cheng Yang, Hsinchu County (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 24, 2022, as Appl. No. 17/582,001.
Claims priority of provisional application 63/230,063, filed on Aug. 6, 2021.
Prior Publication US 2023/0038021 A1, Feb. 9, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 23/522 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 43/10 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first signal line and a second signal line;
a first memory cell coupled to the first signal line;
a plurality of second memory cells, each of the second memory cells having a first terminal coupled to the first signal line through the first memory cell and a second terminal coupled to the second signal line;
a first conductive pillar, coupled to the first signal line, and including a first terminal of the first memory cell; and
a second conductive pillar, including a plurality of portions being the first terminals of the second memory cells and a second terminal of the first memory cell, respectively,
wherein a channel layer of the first memory cell has a first end and a second end, the first end of the channel layer is coupled to the first signal line through the first conductive pillar, and the second end of the channel layer is coupled to the first terminal of each of the second memory cells through the second conductive pillar.