| CPC H10B 43/27 (2023.02) [H10B 43/40 (2023.02); H10B 43/50 (2023.02)] | 19 Claims |

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1. A three-dimensional semiconductor memory device, comprising:
a substrate comprising a cell array region and an extension region;
a peripheral circuit structure comprising a plurality of peripheral transistors on the substrate;
a stack structure comprising a plurality of interlayer dielectric layers and a plurality of gate electrodes that are alternately stacked on the peripheral circuit structure;
a plurality of contacts that penetrate the stack structure on the extension region and are electrically connected with the plurality of peripheral transistors, each of the plurality of contacts comprising a protruding part and a vertical part, the protruding part contacting a sidewall of one of the plurality of gate electrodes, and the vertical part penetrating the stack structure;
a plurality of dielectric patterns between the vertical part and respective sidewalls of the plurality of gate electrodes; and
a barrier layer that conformally extends on a top surface and a bottom surface of each of the gate electrodes,
wherein a top surface and a bottom surface of each of the plurality of dielectric patterns are respectively in contact with adjacent ones of the plurality of interlayer dielectric layers, and
wherein the barrier layer extends along a sidewall of each of the dielectric patterns.
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