| CPC H10B 43/27 (2023.02) | 20 Claims |
|
1. A method, comprising:
forming a plurality of memory cells, comprising:
a plurality of first conductive lines over a substrate;
charge-trapping layers coupled to the first conductive lines;
channel layers arranged adjacent to the charge-trapping layers; and
a plurality of first filling regions arranged between the channel layers;
etching the first filling regions to form first trenches;
depositing a liner over upper surfaces of the charge-trapping layers and the channel layers and sidewalls of the first trenches;
forming second filling regions in the first trenches;
patterning the second filling regions to form second trenches;
depositing a partition region in each of the second trenches; and
removing the liner to expose the charge-trapping layers and the channel layers.
|