US 12,302,560 B2
Three-dimensional memory device with divided drain select gate lines and method for forming the same
Di Wang, Wuhan (CN); Yan Gu, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Wenxi Zhou, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jan. 4, 2022, as Appl. No. 17/568,630.
Application 17/568,630 is a continuation of application No. PCT/CN2021/137400, filed on Dec. 13, 2021.
Prior Publication US 2023/0189521 A1, Jun. 15, 2023
Int. Cl. H10B 43/20 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01)
CPC H10B 43/20 (2023.02) [H10D 30/696 (2025.01); H10D 64/037 (2025.01); H10D 64/679 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a stack structure over a substrate;
a channel structure extending in the stack structure;
a dielectric layer over the channel structure, the dielectric layer comprising a first dielectric material;
a drain-select gate (DSG) cut structure comprising a second dielectric material different from the first dielectric material; and
a contact over the channel structure, the contact extending into the dielectric layer and contacting the DSG cut structure,
wherein:
the DSG cut structure is in contact with the channel structure and one or more conductive layers of the stack structure and in no contact with another channel structure in a cross-section of the channel structure perpendicular to a lateral direction along which the DSG cut structure extends; and
a bottommost surface of the contact is in direct contact with a top surface of a channel plug over the channel structure.