| CPC H10B 41/44 (2023.02) [H10B 41/20 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02)] | 20 Claims |

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1. A three-dimensional memory, comprising:
a stack structure comprising gate line layers and dielectric layers stacked alternatively in a vertical direction;
a dummy structure penetrating through the stack structure in the vertical direction and comprising a first dummy section and a second dummy section; and
a gate line slit penetrating through the stack structure in the vertical direction, wherein the gate line slit has one end extending into at least one gap formed by at least one of the first dummy section or the second dummy section, and the one end is in contact with a portion of the stack structure located in the at least one gap.
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16. A method of manufacturing a three-dimensional memory, comprising:
forming a stack structure on a substrate, the stack structure comprising gate line sacrificial layers and dielectric layers stacked alternatively in a vertical direction;
forming a dummy structure penetrating through the stack structure in the vertical direction and comprising a first dummy section and a second dummy section; and
forming a gate line slit penetrating through the stack structure in the vertical direction, wherein the gate line slit has one end extending into a gap formed by the first dummy section and/or the second dummy section, and the one end is in contact with a portion of stack structure located in the gap.
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