US 12,302,557 B2
Three-dimensional memory device and method of manufacture
Bo-Feng Young, Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); Chi On Chui, Hsinchu (TW); Chun-Chieh Lu, Taipei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,092.
Application 18/362,092 is a division of application No. 17/076,505, filed on Oct. 21, 2020, granted, now 11,765,892.
Prior Publication US 2023/0413544 A1, Dec. 21, 2023
Int. Cl. G11C 7/18 (2006.01); G11C 8/14 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor substrate;
a first memory cell over the semiconductor substrate, the first memory cell comprising a first channel region;
a second memory cell over the first memory cell, the second memory cell comprising a second channel region over the first channel region;
a memory film layer surrounding the first channel region and the second channel region;
a wrap-around word line surrounding the memory film layer;
a stack of source lines on a first side of the first channel region, wherein a first portion of a first source line of the stack of source lines is in contact with the first channel region; and
a stack of bit lines on a second side of the first channel region opposite the first side, wherein a first portion of a first bit line of the stack of bit lines is in contact with the first channel region, wherein the first portion of the first source line has a larger width than other portions of the first source line, and wherein the first portion of the first bit line has a larger width than other portions of the first bit line.