US 12,302,553 B2
Vertical DRAM structure and method
Chia-Ta Yu, New Taipei (TW); Bo-Feng Young, Taipei (TW); Hung Wei Li, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 10, 2022, as Appl. No. 17/668,770.
Claims priority of provisional application 63/211,730, filed on Jun. 17, 2021.
Prior Publication US 2022/0406784 A1, Dec. 22, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 29/10 (2006.01)
CPC H10B 12/315 (2023.02) [H01L 29/1037 (2013.01); H10B 12/033 (2023.02); H10B 12/48 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a conductive line in a substrate;
depositing an insulating layer over the substrate;
patterning a first opening in the insulating layer, the first opening extending perpendicular to the conductive line;
forming a conductive structure in the first opening;
patterning a second opening in the insulating layer, the second opening exposing a sidewall of the conductive structure and the conductive line;
depositing a channel layer in the second opening;
depositing a gate dielectric layer over the channel layer;
depositing a gate electrode over the gate dielectric layer;
recessing the gate dielectric layer, the gate electrode, and the conductive structure, the channel layer extending above the gate electrode; and
depositing an isolation structure surrounding the channel layer, the isolation structure having an upper surface level with an upper surface of the channel layer.