US 12,302,552 B2
Memory cell and semiconductor memory device with the same
Seung Hwan Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 12, 2024, as Appl. No. 18/411,031.
Application 18/411,031 is a continuation of application No. 17/368,376, filed on Jul. 6, 2021, granted, now 11,910,590.
Claims priority of application No. 10-2021-0014052 (KR), filed on Feb. 1, 2021.
Prior Publication US 2024/0147694 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 12/00 (2023.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01)
CPC H10B 12/30 (2023.02) [H10B 12/50 (2023.02); H10D 30/6713 (2025.01); H10D 30/6741 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate;
an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, wherein the active layer comprises a first source/drain region at a side facing a bit line and a second source/drain region at another side facing a capacitor;
the bit line extending in a vertical direction that is perpendicular to the substrate and coupled to the first source/drain region;
a storage contact node coupled to the second source/drain region of the active layer;
the capacitor coupled to the storage contact node; and
a word line extending in a direction crossing the active layer.