US 12,302,551 B2
Semiconductor memory device and method of fabricating the same
Kiseok Lee, Hwaseong-si (KR); and Keunnam Kim, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 17, 2022, as Appl. No. 17/745,960.
Claims priority of application No. 10-2021-0155938 (KR), filed on Nov. 12, 2021.
Prior Publication US 2023/0157002 A1, May 18, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/05 (2023.02); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a stack including layer groups vertically stacked on a substrate, each of the layer groups including a word line, a lower channel layer, an upper channel layer, and a data storing element electrically connected to the lower channel layer and the upper channel layer; and
a bit line at a side of the stack, the bit line extending vertically,
wherein:
the bit line includes a protruding portion connected to the lower channel layer and the upper channel layer of each layer group,
the word line of each layer group extends in a first direction parallel to a top surface of the substrate, and
the word line of each layer group is sandwiched between the lower channel layer and the upper channel layer of the layer group.