US 12,302,550 B2
Semiconductor memory device including capacitor with a dielectric film on an upper plate region, a lower plate region, and a side surface of a connecting region therebetween
Seung Jae Jung, Suwon-si (KR); Jae Hoon Kim, Seoul (KR); Kwang-Ho Park, Cheonan-si (KR); and Yong-Hoon Son, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 21, 2022, as Appl. No. 17/699,839.
Application 17/699,839 is a continuation of application No. 17/038,606, filed on Sep. 30, 2020, granted, now 11,315,929.
Claims priority of application No. 10-2020-0018974 (KR), filed on Feb. 17, 2020.
Prior Publication US 2022/0208768 A1, Jun. 30, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 25/18 (2023.01); H10D 86/80 (2025.01); H10D 87/00 (2025.01)
CPC H10B 12/30 (2023.02) [H10B 12/20 (2023.02); H10B 12/312 (2023.02); H10D 86/80 (2025.01); H01L 25/18 (2013.01); H10D 87/00 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a substrate;
a bit line on the substrate and extending in a vertical direction perpendicular to a top surface of the substrate;
semiconductor patterns spaced apart from each other in the vertical direction and extending in a first horizontal direction parallel to the top surface of the substrate, each of the semiconductor patterns including a first end connected to the bit line and a second end that is opposite to the first end in the first horizontal direction;
gate electrodes extending in a second horizontal direction parallel to the top surface of the substrate and different from the first horizontal direction, each of the gate electrodes including an upper gate electrode and a lower gate electrode, wherein each of the semiconductor patterns is between the lower gate electrode and the upper gate electrode of each of the gate electrodes;
a capacitor including a first electrode that is connected to the second end of the semiconductor patterns, a dielectric film that is on the first electrode, and a second electrode that is on the dielectric film;
a first spacer between the bit line and the gate electrodes; and
a second spacer between the first electrode and the gate electrodes,
wherein the first electrode includes an upper plate region, a lower plate region, and a connecting region between the upper plate region and the lower plate region,
the upper plate region and the lower plate region of the first electrode extend in the second horizontal direction,
the connecting region of the first electrode extends in the vertical direction,
each of the upper plate region and the lower plate region of the first electrode includes a top surface, a bottom surface and a side surface connecting the top surface and the bottom surface, and
the dielectric film extends on the top surface, the side surface and the bottom surface of each of the upper plate region and the lower plate region of the first electrode, and a side surface of the connecting region of the first electrode.