US 12,302,549 B2
Semiconductor memory structure
Shuai Guo, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Apr. 29, 2022, as Appl. No. 17/661,349.
Claims priority of application No. 202111296771.6 (CN), filed on Nov. 2, 2021.
Prior Publication US 2023/0138466 A1, May 4, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 5 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a bit line layer, located in the substrate;
a word line stack layer, located on the substrate, wherein the word line stack layer comprises a word line layer, wherein the word line stack layer further comprises:
a first insulating layer, located on the bit line layer, a second insulating layer, located under the word line layer and a dielectric layer, located on the word line layer;
a transistor comprises a source, a channel region and a drain sequentially stacked on a bit line from the bit line layer, wherein the source penetrating the first insulating layer and the second insulating layer, the channel region penetrating the word line layer, and the drain penetrating the dielectric layer, the source of the transistor is connected to the bit line; and
a gap, located between the first insulating layer and the second insulating layer, wherein the gap is in direct contact with and surrounds the source.