| CPC H10B 12/20 (2023.02) [G11C 5/063 (2013.01); G11C 7/1096 (2013.01); H10B 99/20 (2023.02); H10D 84/138 (2025.01); G11C 11/404 (2013.01); H10D 18/00 (2025.01)] | 12 Claims |
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1. A memory device using a semiconductor element, the memory device comprising:
a substrate;
a first semiconductor layer on the substrate;
a groove having a column shape and extending in a vertically downward direction from a surface of the first semiconductor layer;
a first insulating layer covering a sidewall of the groove except for a bottom part;
a first impurity layer contacting the first semiconductor layer and the first insulating layer near the bottom part of the groove;
a second impurity layer contacting the first impurity layer and the first insulating layer inside the groove;
a second insulating layer coating the surface of the first semiconductor layer and a surface of the first insulating layer except for the second impurity layer;
a second semiconductor layer contacting the second impurity layer and the second insulating layer;
a first gate insulating layer surrounding part or entire of the second semiconductor layer;
a first gate conductor layer covering part or past entire of the first gate insulating layer;
a third impurity layer and a fourth impurity layer disposed on the second semiconductor layer and contacting a side surface of the second semiconductor layer outside respective ends of the first gate conductor layer;
a first wire conductor layer connected to the third impurity layer;
a second wire conductor layer connected to the fourth impurity layer;
a third wire conductor layer connected to the first gate conductor layer; and
a fourth wire conductor layer connected to the first semiconductor layer, wherein memory write operation is performed by controlling voltage applied to the first wire conductor layer, the second wire conductor layer, the third wire conductor layer, and the fourth wire conductor layer to perform operation of generating electrons and holes in the second semiconductor layer and the second impurity layer by an impact ionization phenomenon with current flowing between the third impurity layer and the fourth impurity layer or by gate-induced drain leakage current, operation of removing the electrons or holes that are minority carriers in the second semiconductor layer and the second impurity layer among the generated electrons and holes, and operation of leaving, in the second semiconductor layer and the second impurity layer, some or all of the electrons or holes that are majority carriers in the second semiconductor layer and the second impurity layer, and
memory erase operation is performed by controlling voltage applied to the first wire conductor layer, the second wire conductor layer, the third wire conductor layer, and the first semiconductor layer to remove the left electrons or holes that are majority carriers in the second semiconductor layer from at least one of the first impurity layer, the third impurity layer, and the fourth impurity layer.
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