US 12,302,546 B2
Semiconductor memory structure
Hao-Chuan Chang, Taichung (TW)
Assigned to WINBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Aug. 19, 2022, as Appl. No. 17/891,925.
Claims priority of application No. 111100159 (TW), filed on Jan. 4, 2022.
Prior Publication US 2023/0217641 A1, Jul. 6, 2023
Int. Cl. H10B 12/00 (2023.01); G11C 5/06 (2006.01)
CPC H10B 12/00 (2023.02) [G11C 5/063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory structure, comprising:
a semiconductor substrate;
a bit line disposed on the semiconductor substrate;
a dielectric liner disposed on a sidewall of the bit line, wherein the dielectric liner comprises:
a first nitride liner disposed on a sidewall of the bit line;
an oxide liner disposed on a sidewall of the first nitride liner; and
a second nitride liner disposed on a sidewall of the oxide liner; and
a capacitor contact disposed on a side of the bit line, wherein the capacitor contact comprises:
a semiconductor plug disposed on the semiconductor substrate;
a metal plug disposed on the semiconductor plug;
a metal silicide liner comprising a sidewall portion and a bottom portion respectively extending along a sidewall and a bottom of the metal plug, wherein the sidewall portion is disposed directly above the second nitride liner; and
a nitride layer disposed on the metal silicide liner.