US 12,302,545 B2
Thin film transistor random access memory
Richard E. Fackenthal, Carmichael, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 18, 2023, as Appl. No. 18/369,606.
Application 18/369,606 is a division of application No. 17/191,446, filed on Mar. 3, 2021, granted, now 11,770,923.
Prior Publication US 2024/0081036 A1, Mar. 7, 2024
Int. Cl. H10B 10/00 (2023.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10B 10/125 (2023.02) [H01L 23/528 (2013.01); H10D 30/031 (2025.01); H10D 30/6728 (2025.01); H10D 84/0186 (2025.01); H10D 84/0195 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory cell comprising:
a first transistor comprising a first gate portion coupled with a first access line and a first channel portion coupled between a second access line and a first node of the memory cell, the first channel portion comprising a first pillar formed over a substrate;
a second transistor comprising a second gate portion coupled with a second node of the memory cell and a second channel portion coupled between the first node and a third node of the memory cell, the second channel portion comprising a second pillar formed over the substrate;
a third transistor comprising a third gate portion coupled with the first node and a third channel portion coupled between the third node and the second node, the third channel portion comprising a third pillar formed over the substrate; and
a fourth transistor comprising a fourth gate portion coupled with the first access line and a fourth channel portion coupled between the second node and a third access line, the fourth channel portion comprising a fourth pillar formed over the substrate.