| CPC H10B 10/12 (2023.02) | 4 Claims |
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1. A CMOS SRAM cell having a trench structure, the CMOS SRAM cell comprising:
a semiconductor substrate of first polarity having one polarity,
multiple diffusion regions being formed to be spaced apart from each other as vertical structures having predetermined cross-sections and predetermined depths from a surface of the semiconductor substrate, with the multiple diffusion regions having second polarity opposite to the polarity of the semiconductor substrate and the same first polarity as the polarity of the semiconductor substrate,
multiple electrodes formed on upper parts of the diffusion regions, with each of the multiple electrodes configured to operate as a source electrode, a drain electrode, or a substrate electrode of a MOSFET by applying each signal voltage,
multiple trenches formed to be spaced apart from each other by having predetermined cross-sections and predetermined depths from the surface of the semiconductor substrate,
an insulating layer formed on a surface of each of the trenches from the surface of the semiconductor substrate,
a conductive material filled in the trench inside the insulating layer, and
a MOSFET formed on an upper part of the trench filled with the conductive material and having a gate electrode of the MOSFET to which each signal voltage is applied.
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