| CPC H10B 10/12 (2023.02) [H01L 23/5283 (2013.01); H01L 27/0886 (2013.01)] | 20 Claims |
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1. A device, comprising:
a semiconductor substrate;
a device-level contact over the semiconductor substrate;
a first gate structure and a second gate structure each adjacent the device-level contact and each extending along a first direction over the semiconductor substrate, wherein the first gate structure is aligned lengthwise with the second gate structure;
a dielectric feature between the first gate structure and the second gate structure and having a top surface extending along a first plane, wherein a first sidewall of the dielectric feature defines an end-wall of the first gate structure, and a second sidewall of the dielectric feature defines an end-wall of the second gate structure;
a conductive line extending along a second direction over the device-level contact and over the dielectric feature, wherein a projection of the conductive line along a third direction onto the first plane passes between the first sidewall and the second sidewall of the dielectric feature, the third direction extending perpendicular to the first plane; and
a via feature vertically connecting the device-level contact and the conductive line,
wherein the via feature interfaces with the device-level contact along a second plane extending parallel to a top surface of the semiconductor substrate; and
wherein the via feature has a first dimension along the second direction on the second plane, the device-level contact has a second dimension along the second direction on the second plane, and the first dimension is greater than the second dimension.
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