CPC H04W 92/18 (2013.01) [H04L 1/1854 (2013.01)] | 19 Claims |
1. A device comprising:
a processor circuit and a memory circuit, wherein the memory is arranged to store instructions for the processor circuit,
wherein the processor circuit is arranged to communicate using a portion of a plurality sidelink resources,
wherein the processor circuit is arranged to receive a sidelink feedback from a receiving device,
wherein the sidelink feedback indicates a successful or non-successful reception by the receiving device,
wherein the processor circuit is arranged to report the sidelink feedback to a third device,
wherein the third device is arranged to provide to sidelink resources for a possible retransmission of a data packet in response to the sidelink feedback,
wherein the processor circuit is arranged to reporting the sidelink feedback is activated or deactivated in response to at least one conditions,
wherein the processor circuit is arranged to deactivate the sidelink feedback reporting in response to a deactivation signal from the third device,
wherein the processor circuit is arranged to switch to an out-of-coverage sidelink feedback procedure in response to the deactivation signal from the third device.
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