US 12,302,299 B2
Slot format indicator configurations
Ahmed Abdelaziz Ibrahim Abdelaziz Zewail, San Diego, CA (US); Qingjiang Tian, San Diego, CA (US); Jing Sun, San Diego, CA (US); Wooseok Nam, San Diego, CA (US); Xiaoxia Zhang, San Diego, CA (US); and Tao Luo, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 17, 2022, as Appl. No. 17/651,497.
Claims priority of provisional application 63/187,038, filed on May 11, 2021.
Prior Publication US 2022/0369316 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 72/0453 (2023.01); H04W 72/0446 (2023.01); H04W 72/23 (2023.01)
CPC H04W 72/0453 (2013.01) [H04W 72/0446 (2013.01); H04W 72/23 (2023.01)] 29 Claims
OG exemplary drawing
 
1. A user equipment (UE), comprising:
one or more memories; and
one or more processors coupled to the one or more memories, the one or more processors individually or collectively configured to cause the UE to:
receive, from a network entity, an indication of a slot format indicator (SFI) configuration for a plurality of slots, the SFI configuration including a first SFI associated with a first subset of the plurality of slots and a second SFI associated with a second subset of the plurality of slots, wherein:
the SFI configuration designates an SFI slot pattern comprising the first and second SFIs that repeats at least partially across the plurality of slots, and
upon reaching a respective slot repetition factor for a respective SFI, the respective SFI is removed from the SFI slot pattern for any subsequent repetitions of the SFI slot pattern; and
communicate with the network entity on one or more of the plurality of slots in accordance with the SFI configuration.