CPC H04W 56/001 (2013.01) [H04L 27/2613 (2013.01); H04L 27/2634 (2013.01); H04W 4/80 (2018.02); H04L 27/26132 (2021.01)] | 24 Claims |
1. A device comprising:
a transmit circuit; and
a processor coupled to the transmit circuit, wherein the processor is configured to:
generate a first set of data symbols based on a second set of data symbols such that the first set of data symbols does not include complex symbols,
generate a header that includes a short training field and a long training field based on symbols of the first set of data symbols, wherein the short training field and the long training field are adjacent to one another in the header, and wherein the short training field comprises a group of bits that are repeated, and wherein a last group of bits of the short training field are negated,
generate a packet that includes the header and a packet payload, and
transmit the packet using the transmit circuit.
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