| CPC H04W 28/0257 (2013.01) [H04W 28/0268 (2013.01); H04W 72/0453 (2013.01); H04W 72/21 (2023.01); H04W 72/56 (2023.01)] | 18 Claims |

|
10. An uplink data transmission control apparatus, comprising:
at least one processor, wherein the at least one processor is coupled to at least one memory storing programming instructions executable by the at least one processor to perform operations comprising:
receiving first information from a network device, wherein the first information indicates an uplink maximum bit rate of each of at least one logical channel; and
allocating an uplink resource to one or more logical channels in the at least one logical channel based on the uplink maximum bit rate, wherein the at least one logical channel comprises a first logical channel, wherein a first service data unit (SDU) is on the first logical channel and is not multiplexed into a protocol data unit (PDU), wherein a second SDU is on the first logical channel and has been multiplexed into the PDU, and wherein the allocating comprises:
if a sum of an uplink bit rate of the first SDU and an uplink bit rate of the second SDU is greater than an uplink maximum bit rate of the first logical channel:
performing segmentation processing on the first SDU to obtain a first sub-SDU; and
multiplexing the first sub-SDU into the PDU.
|