US 12,302,064 B2
Configurable microphone using internal clock changing
Dietmar Straeussnigg, Villach (AT); and Daniel Neumaier, Feldkirchen (AT)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on May 11, 2020, as Appl. No. 16/871,546.
Application 16/871,546 is a continuation in part of application No. 16/773,079, filed on Jan. 27, 2020.
Prior Publication US 2021/0235200 A1, Jul. 29, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 3/00 (2006.01); H04R 3/00 (2006.01); H04R 19/04 (2006.01)
CPC H04R 19/04 (2013.01) [H04R 3/00 (2013.01); H04R 2201/003 (2013.01); H04R 2430/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a digital device, the method comprising:
in a first operational mode, converting an analog output of a microelectromechanical system (MEMS) into a first internal data stream having a first sampling rate derived from a clock frequency of an undivided clock signal and a first external data stream having the first sampling rate;
transitioning from the first operational mode to a second operational mode without restarting the MEMS;
in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, filtering the second internal data stream, and after filtering the second internal data stream, performing a sampling rate conversion of the second internal data stream to generate a second external data stream having the first sampling rate, wherein the second sampling rate is derived from a clock frequency of a divided clock signal;
inputting the undivided clock signal into a first input of a multiplexer;
inputting the undivided clock signal into a clock divider to generate the divided clock signal;
inputting the divided clock signal into a second input of the multiplexer; and
inputting a control signal to a control input of the multiplexer, the control signal indicating one of the first and second operational modes,
wherein, in the first operational mode, the multiplexer couples the first input of the multiplexer to an output of the multiplexer, wherein, in the second operational mode, the multiplexer couples the second input of the multiplexer to the output of the multiplexer, and wherein the output of the multiplexer provides the undivided clock signal in the first operational mode and provides the divided clock signal in the second operational mode.