	US 12,302,022 B2
	Analog-to-digital conversion circuit, solid-state image sensor, and method for controlling analog-to-digital conversion circuit
Yuki Ozawa, Kanagawa (JP); Hiromu Kato, Kanagawa (JP); and Atsushi Suzuki, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/245,567
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Aug. 11, 2021, PCT No. PCT/JP2021/029605 § 371(c)(1), (2) Date Mar. 16, 2023, PCT Pub. No. WO2022/074931, PCT Pub. Date Apr. 14, 2022.
Claims priority of application No. 2020-168978 (JP), filed on Oct. 6, 2020.
Prior Publication US 2023/0370746 A1, Nov. 16, 2023
Int. Cl. H04N 25/772 (2023.01); H03M 1/34 (2006.01); H03M 1/50 (2006.01)

CPC H04N 25/772 (2023.01) [H03M 1/34 (2013.01); H03M 1/50 (2013.01)]

11 Claims

1. An analog-to-digital conversion circuit, comprising:

a comparator configured to:

compare a first analog signal and a specific reference signal;

output a comparison result associated with the comparison of the first analog signal and the specific reference signal; and

invert the comparison result;

a counter configured to:

count a specific count value; and

output a bit string that indicates the specific count value;

a time-to-digital converter configured to:

determine a first value by a least significant bit of the bit string; and

convert a first time period into a digital signal, wherein

the first time period starts from a first time and ends at a second time,

the first time is associated with the inverted comparison result,

the second time is associated with the determined first value,

the time-to-digital converter includes a ring oscillator, and

the ring oscillator is configured to generate an alternating current signal;

an oscillation frequency adjustment unit that comprises a frequency divider wherein

the frequency divider is configured to divide a frequency of the alternating current signal; and

a holding unit configured to hold the bit string at the first time.