US 12,302,017 B2
Solid-state imaging device
Mamoru Sato, Kanagawa (JP); Akihiko Kato, Tokyo (JP); and Yusuke Oike, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Oct. 24, 2022, as Appl. No. 17/971,981.
Application 17/971,981 is a continuation of application No. 16/976,361, granted, now 11,553,148, previously published as PCT/JP2019/000550, filed on Jan. 10, 2019.
Claims priority of application No. 2018-072215 (JP), filed on Apr. 4, 2018.
Prior Publication US 2023/0041457 A1, Feb. 9, 2023
Int. Cl. H04N 25/673 (2023.01); H04N 25/63 (2023.01); H04N 25/633 (2023.01); H04N 25/677 (2023.01); H04N 25/778 (2023.01); H04N 25/74 (2023.01); H04N 25/79 (2023.01)
CPC H04N 25/673 (2023.01) [H04N 25/63 (2023.01); H04N 25/633 (2023.01); H04N 25/677 (2023.01); H04N 25/778 (2023.01); H04N 25/74 (2023.01); H04N 25/79 (2023.01)] 6 Claims
OG exemplary drawing
 
1. A solid-state imaging device comprising:
a pixel array including a plurality of rows, each row including a plurality of pixels, each of the pixels including a photoelectric conversion unit and a transfer transistor;
a readout row selection circuit configured to select a readout row from among the plurality of rows every time a predetermined period elapses and cause each of the plurality of pixels in the readout row to generate a signal potential according to a received light amount;
a reference row selection circuit configured to select a row different from a previous row from among the plurality of rows as a current reference row every time the predetermined period elapses, and cause each of the plurality of pixels in the reference row to generate a reference potential; and
a readout circuit configured to read a signal according to a difference between the signal potential and the reference potential, wherein
the plurality of rows includes effective pixel rows that include effective pixels that perform photoelectric conversion and dummy pixel rows that include dummy pixels,
the dummy pixel rows are arranged in a light shielding region that inhibits photoelectric conversion,
the readout row selection circuit selects one of the effective pixel rows as the readout row,
the reference row selection circuit selects one of the dummy pixel rows as the reference row,
each of the plurality of pixels in the readout row includes a readout-side amplification transistor electrically connected to the photoelectric conversion unit via the transfer transistor,
each of the plurality of pixels in the reference row includes a reference-side amplification transistor electrically connected to the photoelectric conversion unit via the transfer transistor,
an input signal is input to the readout-side amplification transistors and the reference-side amplification transistor via a sample-hold circuit,
an output of a differential amplification circuit is applied to the sample-hold circuit on a side of the readout-side amplification transistor as a negative feedback, and
an arbitrary voltage is set for the sample-hold circuit on a side of the reference-side amplification transistor.