| CPC H04L 9/32 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0637 (2013.01); G06F 3/0673 (2013.01)] | 20 Claims |

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1. An electronic device comprising:
a memory; and
at least one processor configured to be operatively connected to the memory,
wherein the memory stores instructions which, when executed by the at least one processor, cause the processor to:
allocate a first address space and a second address space to the memory in a rich execution environment (REE) based on detecting a request to write data to the memory,
write the data to the first address space of the memory and then detect access to the second address space in the REE,
configure an access permission of a first user virtual memory address space, mapped to the first address space in the memory, in the REE so that write access is deactivated by a trusted execution environment (TEE) manager based on detecting the access to the second address space, and configure an access permission of a second user virtual memory address space, mapped to the second address space, in the REE so that read access is activated and write access is deactivated, and
configure an access permission of a first kernel virtual memory address space, mapped to the first address space in the memory, in the REE so that write access is deactivated by the TEE manager.
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