US 12,301,256 B2
Resource efficient list decoding operations
Yevgeny Zagalsky, Karmey Yosef (IL); Peer Berger, Hod Hasharon (IL); Ran Berliner, Kfar Aviv (IL); Shay Landis, Hod Hasharon (IL); Eitan Yerushalmi, Tel Aviv (IL); and David Jacobian, Herzliya (IL)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by Qualcomm Incorporated, San Diego, CA (US)
Filed on Aug. 16, 2023, as Appl. No. 18/234,824.
Prior Publication US 2025/0062780 A1, Feb. 20, 2025
Int. Cl. H03M 13/15 (2006.01); H03M 13/11 (2006.01); H03M 13/41 (2006.01)
CPC H03M 13/1555 (2013.01) [H03M 13/1125 (2013.01); H03M 13/4115 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus configured for wireless communications, comprising:
one or more memories comprising processor-executable instructions; and
one or more processors configured to execute the processor-executable instructions and cause the apparatus to:
receive a codeword comprising a plurality of channel bits encoded with an error-correcting code, the plurality of channel bits comprising, at least, a plurality of information bits;
determine a payload size of the codeword;
determine a channel capacity metric for the plurality of channel bits;
determine a minimal list size for a list decoding operation based on at least the payload size and the channel capacity metric; and
perform the list decoding operation on the codeword based on the minimal list size to obtain the plurality of information bits.