US 12,301,233 B2
Ultra low latency pattern matching system and method
Igor G. Muskatblit, Mountain View, CA (US); Michael Gorbovitski, New York, NY (US); and Joshua N. Elijah, London (GB)
Assigned to Morgan Stanley Services Group Inc., New York, NY (US)
Filed by Morgan Stanley Services Group Inc., New York, NY (US)
Filed on Aug. 6, 2024, as Appl. No. 18/795,954.
Claims priority of provisional application 63/517,980, filed on Aug. 7, 2023.
Prior Publication US 2025/0055462 A1, Feb. 13, 2025
Int. Cl. G06F 11/00 (2006.01); H03K 19/17704 (2020.01); H03K 19/17792 (2020.01)
CPC H03K 19/17792 (2013.01) [H03K 19/17708 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A data processing device, comprising:
a data communication port configured to transmit and receive data to and from at least one computing device; and
a replicator configured to receive ingress data from the data communication port and to replicate the received ingress data to a pattern matcher and a field programmable gate array,
wherein the pattern matcher is configured by pattern information received from the field programmable gate array, and further wherein the pattern matcher is configured to generate and transmit, to the field programmable gate array, a trigger signal associated with any of the replicated data received from the replicator that match the pattern information, and;
further wherein the field programmable gate array is configured to perform bit operations on at least some of the replicated data received from the replicator as a function of the trigger signal received from the pattern matcher.