US 12,301,228 B2
Flip-flop device and method of operating flip-flop device
Greg Gruber, Hsinchu (TW); Chi-Lin Liu, New Taipei (TW); Ming-Chang Kuo, Hsinchu County (TW); Lee-Chung Lu, Taipei (TW); and Shang-Chih Hsieh, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Apr. 24, 2024, as Appl. No. 18/644,156.
Application 18/644,156 is a continuation of application No. 18/056,262, filed on Nov. 17, 2022, granted, now 11,996,842.
Application 18/056,262 is a continuation of application No. 17/353,674, filed on Jun. 21, 2021, granted, now 11,509,306, issued on Nov. 22, 2022.
Application 17/353,674 is a continuation of application No. 16/744,836, filed on Jan. 16, 2020, granted, now 11,050,423, issued on Jun. 29, 2021.
Prior Publication US 2024/0275384 A1, Aug. 15, 2024
Int. Cl. H03K 19/00 (2006.01); G01R 31/3185 (2006.01)
CPC H03K 19/0013 (2013.01) [G01R 31/318536 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a flip-flop circuit, arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and
a gating circuit, coupled to the flip-flop circuit, the gating circuit being arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal, wherein when the master signal stays at a first logic level and the input clock signal toggles, one of the first clock signal and the second clock signal stays at a same logic level, and a signal transition of the other of the first clock signal and the second clock signal occurs in response to toggling of the input clock signal;
wherein a number of signal transitions of the first clock signal during a period of time and a number of signal transitions of the second clock signal during the period of time are not greater than a number of signal transitions of the input clock signal during the period of time during the writing mode and the storing mode.