| CPC H03H 11/04 (2013.01) | 20 Claims |
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1. An integrated circuit, comprising:
an input buffer having a first input coupled to an input node to receive an input signal having a plurality of pulse widths and to produce a buffer output;
a slicer having a slicer input, a slicer output signal, and slicer threshold adjustment circuitry to control a boundary for the slicer input meeting a first threshold condition that is to cause the slicer to output a first slicer output signal value and the slicer input meeting a second threshold condition that is to cause the slicer to output a second slicer output signal value;
a resistor-capacitor charging-discharging circuit coupled between the buffer output and the slicer input, the resistor-capacitor charging-discharging circuit calibrated to a first time constant based on timing information;
charging and discharging circuitry to charge and discharge a capacitance of the resistor-capacitor charging-discharging circuit based on the input signal and the slicer output signal value; and
pulse with adjustment circuitry coupled to the slicer.
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