US 12,301,117 B2
Controllers and methods for detecting and adjusting voltage drops related to transistors in power converters
Penglin Yang, Shanghai (CN); Yaming Cao, Shanghai (CN); Yuan Lin, Shanghai (CN); and Lieyi Fang, Shanghai (CN)
Assigned to On-Bright Electronics (Shanghai) Co., Ltd., Shanghai (CN)
Filed by ON-BRIGHT ELECTRONICS (SHANGHAI) CO., LTD., Shanghai (CN)
Filed on Feb. 20, 2023, as Appl. No. 18/111,853.
Claims priority of application No. 202210102629.1 (CN), filed on Jan. 27, 2022.
Prior Publication US 2023/0291315 A1, Sep. 14, 2023
Int. Cl. H02M 3/335 (2006.01); G01R 31/36 (2020.01)
CPC H02M 3/33507 (2013.01) [G01R 31/36 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controller for a power converter, the controller comprising:
a first gate driver configured to output a first drive signal to a first transistor related to a primary winding, the first transistor including a drain terminal and a source terminal, the primary winding being configured to receive an input voltage, the primary being coupled to a first auxiliary winding and a second auxiliary winding;
one or more voltage detectors configured to generate a first detection signal and a second detection signal based at least in part on a current signal related to the first auxiliary winding;
a time controller configured to receive the first detection signal and the second detection signal and generate a control signal based at least in part on the first detection signal and the second detection signal; and
a second gate driver configured to receive the control signal, generate a second drive signal based at least in part on the control signal, and output the second drive signal to a second transistor related to the second auxiliary winding;
wherein the one or more voltage detectors are further configured to:
at a first time when the first drive signal is at a first logic level and the second drive signal is at a second logic level, detect the input voltage based at least in part on the current signal; and
at a second time when the first drive signal is at the second logic level and the second drive signal is also at the second logic level, detect the input voltage minus a voltage drop from the drain terminal to the source terminal of the first transistor based at least in part on the current signal;
wherein the one or more voltage detectors are further configured to:
generate the first detection signal representing the input voltage at the first time; and
generate the second detection signal representing the input voltage minus the voltage drop from the drain terminal to the source terminal of the first transistor at the second time;
wherein the time controller is further configured to:
determine the voltage drop from the drain terminal to the source terminal of the first transistor based at least in part on the first detection signal and the second detection; and
determine a time duration when the second drive signal remains at the first logic level based at least in part on the determined voltage drop from the drain terminal to the source terminal of the first transistor.