US 12,300,811 B2
Lithium-ion battery with thin crystalline anode and methods of making same
Devendra K. Sadana, Pleasantville, NY (US)
Assigned to POSI ENERGY—SILICON POWER, LLC, Pleasantville, NY (US)
Filed by POSI ENERGY-SILICON POWER, LLC, Pleasantville, NY (US); and Devendra K. Sadana, Pleasantville, NY (US)
Filed on Dec. 10, 2021, as Appl. No. 17/547,958.
Application 17/547,958 is a continuation in part of application No. 17/366,521, filed on Jul. 2, 2021.
Claims priority of provisional application 63/136,189, filed on Jan. 11, 2021.
Prior Publication US 2022/0223848 A1, Jul. 14, 2022
Int. Cl. H01M 4/38 (2006.01); H01M 4/02 (2006.01); H01M 4/04 (2006.01); H01M 4/134 (2010.01); H01M 4/36 (2006.01); H01M 4/66 (2006.01); H01M 10/0525 (2010.01)
CPC H01M 4/386 (2013.01) [H01M 4/0426 (2013.01); H01M 4/134 (2013.01); H01M 4/366 (2013.01); H01M 4/382 (2013.01); H01M 4/661 (2013.01); H01M 10/0525 (2013.01); H01M 2004/021 (2013.01); H01M 2300/0091 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A thinned crystalline porous anode structure suitable for use in a lithium-ion battery,
said battery containing a cathode layer and an electrolyte/separator layer disposed in sequence between said cathode layer and said anode structure,
said anode structure comprising:
a non-patterned unitary construction having a single crystalline porous semi-conductive silicon surface region comprising:
a first top porous layer having a first thickness of between about 1 μm and 20 μm; and
a second porous layer located beneath said top porous layer having a porosity between 30% and 50% and forming an interface with said top porous layer with a second thickness of between 1 μm and 50 μm;
said second porous layer being atop and in direct contact forming an interface with a p+ silicon substrate, said p+ silicon substrate having a thickness greater than 200 μm; and
wherein said p+ Si substrate has a resistivity range between 0.05 and 0.005-ohm cm, and surface crystallographic orientations comprising (100), (110), (111), (211), and (311) and,
wherein said p+ silicon substrate is supported by a metal current collector having a thickness of between 1 μm and 50 μm.