US 12,300,745 B2
Compound semiconductor device and method of manufacturing compound semiconductor device
Akito Iwao, Kumamoto (JP); and Yoshikazu Motoyama, Kumamoto (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/758,300
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Nov. 26, 2020, PCT No. PCT/JP2020/044110
§ 371(c)(1), (2) Date Jun. 30, 2022,
PCT Pub. No. WO2021/140776, PCT Pub. Date Jul. 15, 2021.
Claims priority of application No. 2020-001337 (JP), filed on Jan. 8, 2020.
Prior Publication US 2023/0036228 A1, Feb. 2, 2023
Int. Cl. H01L 29/778 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/778 (2013.01) [H01L 29/0607 (2013.01); H01L 29/0843 (2013.01); H01L 29/1095 (2013.01); H01L 29/66431 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A compound semiconductor device, comprising: a laminated body constituted of a compound semiconductor and including a channel layer in which a first conductivity type carrier runs;
a gate electrode provided on an upper surface side of the laminated body;
a source electrode provided on the upper surface side of the laminated body; and
a drain electrode provided on the upper surface side of the laminated body,
the laminated body including:
a second conductivity type first low resistance layer that is provided at a position facing the gate electrode and is in contact with the gate electrode,
a first electric-field relaxation layer extended from the second conductivity type first low resistance layer toward a side of one of the source electrode and the drain electrode and configured to relax electric field concentration to the second conductivity type first low resistance layer, and
a first amorphous layer covering a first side surface that is a side surface of the first electric-field relaxation layer and faces one of the source electrode and the drain electrode.