US 12,300,723 B2
Transistor including downward extending silicide
Jung-Chien Cheng, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); Shi Ning Ju, Hsinchu (TW); Guan-Lin Chen, Hsinchu (TW); Bo-Rong Lin, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 25, 2022, as Appl. No. 17/704,882.
Claims priority of provisional application 63/275,347, filed on Nov. 3, 2021.
Prior Publication US 2023/0134161 A1, May 4, 2023
Int. Cl. H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 29/0649 (2013.01); H01L 29/0665 (2013.01); H01L 29/665 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a substrate; and
a first nanostructure transistor including:
a plurality of first stacked channels;
a source/drain region in contact with the first semiconductor nanostructures and having a sidewall;
a gate electrode above the first stacked channels;
a gate spacer layer on a sidewall of the gate electrode above the stacked channels;
a source/drain contact having a sidewall extending lower than at least one of the first channels; and
a silicide having a first portion in contact with a sidewall of the source/drain region and the sidewall of the source/drain contact and extending lower than at least one of the first channels, and a second portion on a top surface of the source/drain region and in contact with a sidewall of the gate spacer layer.