US 12,300,722 B2
Selective liner on backside via and method thereof
Lin-Yu Huang, Hsinchu (TW); Li-Zhen Yu, Hsinchu (TW); Chia-Hao Chang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 21, 2024, as Appl. No. 18/750,589.
Application 17/750,600 is a division of application No. 16/944,263, filed on Jul. 31, 2020, granted, now 11,342,413, issued on May 24, 2022.
Application 18/750,589 is a continuation of application No. 18/358,576, filed on Jul. 25, 2023, granted, now 12,021,119.
Application 18/358,576 is a continuation of application No. 17/750,600, filed on May 23, 2022, granted, now 11,742,385, issued on Aug. 29, 2023.
Claims priority of provisional application 63/015,322, filed on Apr. 24, 2020.
Prior Publication US 2024/0347598 A1, Oct. 17, 2024
Int. Cl. H01L 29/08 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0843 (2013.01) [H01L 29/0649 (2013.01); H01L 29/785 (2013.01); H01L 23/528 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first source/drain (S/D) feature having a first side and a second side;
a channel layer connected to the first S/D feature between the first side and the second side;
a gate structure engaging the channel layer;
an interconnect structure adjacent the first side of the first S/D feature;
a backside power rail adjacent a second side of the first S/D feature;
a conductive feature extending from the backside power rail to the second side of the first S/D feature; and
a liner layer along sides of the conductive feature, the liner layer having a terminal end covered by the conductive feature.