US 12,300,640 B2
Semiconductor device and method of manufacturing thereof
Tsung-Chieh Hsiao, Shetou Township (TW); Hsiang-Ku Shen, Hsinchu (TW); Yuan-Yang Hsiao, Taipei (TW); Ying-Yao Lai, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 23, 2023, as Appl. No. 18/213,759.
Application 18/213,759 is a division of application No. 17/367,896, filed on Jul. 6, 2021, granted, now 11,728,295.
Claims priority of provisional application 63/166,892, filed on Mar. 26, 2021.
Prior Publication US 2023/0335517 A1, Oct. 19, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/03 (2013.01) [H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01029 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first dielectric layer;
a redistribution layer formed in the first dielectric layer, including a first liner conductive layer, a main conductive layer disposed over the first liner conductive layer, and a cover conductive layer; and
a second dielectric layer disposed over the cover conductive layer and the first dielectric layer,
wherein the main conductive layer is fully wrapped around by the cover conductive layer and the first liner conductive layer.