| CPC H01L 23/5283 (2013.01) [H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 9 Claims |

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1. A three-dimensional memory device, comprising:
a substrate comprising a first region and a second region;
a memory stack structure comprising a plurality of conductive layers and dielectric layers alternately stacked on the substrate and extending from the first region to the second region, wherein the memory stack structure on the second region comprises a staircase structure comprising steps respectively comprising one of the conductive layers and one of the dielectric layers, wherein for each of the steps a sidewall of the conductive layer is recessed from a sidewall of the dielectric layer to form a recess that exposes a bottom surface of a step nosing portion of the dielectric layer;
an interlayer dielectric layer disposed on the staircase structure; and
a plurality of word line contact plugs respectively extending through the interlayer dielectric layer and one of the dielectric layers of the staircase structure to contact one of the conductive layers of the staircase structure, wherein at least one of the word line contact plugs has a first bottom surface directly contacting a top surface of one of the conductive layers and a second bottom surface directly contacting a top surface of one of the step nosing portions.
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