US 12,300,605 B2
Reducing internal node loading in combination circuits
Chien-Yuan Chen, Hsinchu (TW); Cheng-Hung Lee, Hsinchu (TW); Hung-Jen Liao, Hsin-Chu (TW); Hau-Tai Shieh, Hsinchu (TW); Kao-Cheng Lin, Taipei (TW); and Wei-Min Chan, Sindian (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,670.
Application 18/362,670 is a continuation of application No. 17/816,108, filed on Jul. 29, 2022, granted, now 11,854,970.
Application 17/816,108 is a continuation of application No. 17/173,750, filed on Feb. 11, 2021, granted, now 11,450,605, issued on Sep. 20, 2022.
Prior Publication US 2023/0378063 A1, Nov. 23, 2023
Int. Cl. H01L 23/528 (2006.01); G06F 30/392 (2020.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H10B 10/00 (2023.01)
CPC H01L 23/528 (2013.01) [G06F 30/392 (2020.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first active diffusion region serving as a source/drain region for p-type transistors;
a second active diffusion region serving as a source/drain region for n-type transistors;
a plurality of internal nodes formed in the first active diffusion region;
a plurality of poly lines extending across both the first active diffusion region and the second active diffusion region;
a plurality of conductive layers, each of the plurality of conductive layers comprising at least one conductive stripe, wherein the plurality of internal nodes are not connected a common conductive stripe in any of the plurality of conductive layers.