US 12,300,569 B2
Semiconductor device
Masanori Tsukuda, Tokyo (JP); Koichi Nishi, Tokyo (JP); Shinya Soneda, Tokyo (JP); Koji Tanaka, Tokyo (JP); Norikazu Sakai, Tokyo (JP); and Taketoshi Shikano, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Jul. 5, 2022, as Appl. No. 17/857,293.
Claims priority of application No. 2021-201732 (JP), filed on Dec. 13, 2021.
Prior Publication US 2023/0187308 A1, Jun. 15, 2023
Int. Cl. H01L 23/373 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/3735 (2013.01) [H01L 24/48 (2013.01); H01L 2224/48225 (2013.01); H01L 2924/13055 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor chip including a first principal surface and a second principal surface on opposite sides each other;
a first principal electrode formed on the first principal surface and electrically connected to the semiconductor chip;
a first control electrode pad formed on the first principal surface;
a first insulating film formed between the semiconductor chip and the first control electrode pad;
a second principal electrode formed on the second principal surface and electrically connected to the semiconductor chip;
a second control electrode pad formed on the second principal surface;
a second insulating film formed between the semiconductor chip and the second control electrode pad;
a first wire bonded to the first principal electrode;
a second wire bonded to the first control electrode pad; and
an insulating substrate including first and second metal patterns separated from each other,
wherein the second principal electrode and the second control electrode pad are respectively bonded to the first and second metal patterns,
bonding sections of the first and second wires overlap a bonding section of the second principal electrode or the second control electrode pad in plan view, and
thickness of the first and second metal patterns is 0.2 mm or less.