US 12,300,566 B2
Integrated chip with good thermal dissipation performance
Harry-Hak-Lay Chuang, Zhubei (TW); Hsin Fu Lin, Hsinchu County (TW); Shiang-Hung Huang, New Taipei (TW); and Tsung-Hao Yeh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 25, 2022, as Appl. No. 17/728,048.
Claims priority of provisional application 63/222,556, filed on Jul. 16, 2021.
Claims priority of provisional application 63/220,093, filed on Jul. 9, 2021.
Prior Publication US 2023/0010333 A1, Jan. 12, 2023
Int. Cl. H01L 23/367 (2006.01); H01L 21/762 (2006.01); H01L 23/528 (2006.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01)
CPC H01L 23/367 (2013.01) [H01L 21/76283 (2013.01); H01L 23/5283 (2013.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip (IC), comprising:
forming a semiconductor device along a first side of a substrate;
forming a plurality of conductive features within an intermetal dielectric (IMD) structure formed on the first side of the substrate;
forming a passivation layer on the substrate, wherein the passivation layer is formed to continuously extend laterally past opposing sides of the semiconductor device;
forming an opening in the passivation layer, wherein the opening is vertically spaced apart from the semiconductor device;
forming a second semiconductor device within the substrate;
forming a second opening that extends through the passivation layer and the IMD structure, the second opening being directly over the second semiconductor device; and
wherein the opening has a different depth than the second opening.