US 12,300,547 B2
Method of manufacturing semiconductor element and semiconductor element
Kazuki Yamaguchi, Tokushima (JP); and Yoshitaka Sumitomo, Tokushima (JP)
Assigned to NICHIA CORPORATION, Anan (JP)
Filed by NICHIA CORPORATION, Anan (JP)
Filed on Jan. 8, 2024, as Appl. No. 18/407,011.
Application 18/407,011 is a division of application No. 17/327,005, filed on May 21, 2021, granted, now 11,901,233.
Claims priority of application No. 2020-090108 (JP), filed on May 22, 2020; and application No. 2021-075885 (JP), filed on Apr. 28, 2021.
Prior Publication US 2024/0178066 A1, May 30, 2024
Int. Cl. H01L 21/78 (2006.01); B23K 26/40 (2014.01); B23K 26/53 (2014.01); H01L 23/544 (2006.01); B23K 101/40 (2006.01)
CPC H01L 21/78 (2013.01) [B23K 26/40 (2013.01); B23K 26/53 (2015.10); H01L 23/544 (2013.01); B23K 2101/40 (2018.08)] 4 Claims
OG exemplary drawing
 
1. A semiconductor element comprising:
a substrate having a first surface, a second surface, and at least one lateral surface; and
a semiconductor layer formed on the second surface,
wherein the at least one lateral surface includes:
at least one flat region,
a first region that extends along a first direction parallel to the first surface at a position apart from the first surface and the second surface, wherein a surface roughness of the first region is larger than a surface roughness of the flat region, and
a second region that extends along the first direction parallel to the first surface at a position between the first region and the first surface and apart from the first surface, wherein a surface roughness of the second region is larger than the surface roughness of the flat region, and
wherein the substrate includes, in an interior of the substrate, a plurality of modified portions aligned along the first direction at a position shifted from the first region in a second direction that intersects the first direction and is parallel to the first surface.