US 12,300,543 B2
Method for manufacturing a semiconductor device having a dummy section
Osamu Koike, Yokohama (JP); and Yutaka Kadogawa, Yokohama (JP)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/360,814.
Application 17/117,727 is a division of application No. 16/460,969, filed on Jul. 2, 2019, granted, now 10,892,189, issued on Jan. 12, 2021.
Application 16/460,969 is a division of application No. 15/879,006, filed on Jan. 24, 2018, abandoned.
Application 15/879,006 is a division of application No. 12/458,324, filed on Jul. 8, 2009, granted, now 9,892,968, issued on Feb. 13, 2018.
Application 18/360,814 is a continuation of application No. 17/117,727, filed on Dec. 10, 2020, granted, now 11,798,847.
Claims priority of application No. 2008-180289 (JP), filed on Jul. 10, 2008.
Prior Publication US 2023/0386922 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 23/48 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 27/146 (2006.01)
CPC H01L 21/76898 (2013.01) [H01L 21/76224 (2013.01); H01L 21/76819 (2013.01); H01L 23/481 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/76229 (2013.01); H01L 27/14636 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13024 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor substrate having an obverse surface and a reverse surface opposite to the obverse surface;
a plurality of active elements on the obverse surface to define an element-absence area provided adjacent to the active elements on the obverse surface, the element-absence area being free of any of the active elements;
a first insulating film formed over the active elements and the element-absence area;
an electrode pad which is provided inside the first insulating film and is electrically connected to one or more of the active elements, the element-absence area further including:
a second insulating film for forming a shallow trench isolation, the second insulating film being disposed on the obverse surface and under the first insulating film;
a ring-shaped dummy portion made of the same material as the semiconductor substrate, wherein an inner edge of the ring-shaped dummy portion is circular from a plan view; and
a plurality of island-shaped dummy portions made of the same material as the semiconductor substrate, the ring-shaped dummy portion and each of the island-shaped dummy portions being disposed on the obverse surface and in the second insulating film, the ring-shaped dummy portion and each of the island-shaped dummy portions have top surfaces coplanar with a top surface of the second insulating film, and a maximum distance of an outer edge of the ring-shaped dummy portion to a closest point on the inner edge of the ring-shaped dummy portion in the plan view is larger than a width of each of the island-shaped dummy portions in the plan view;
a Through Silicon VIA electrode penetrating through the semiconductor substrate from the reverse surface of the semiconductor substrate to the obverse surface.