US 12,300,314 B2
Memory system and memory device
Naomi Takeda, Yokohama (JP); Masanobu Shirakawa, Chigasaki (JP); and Akio Sugahara, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on May 28, 2024, as Appl. No. 18/675,257.
Application 18/675,257 is a continuation of application No. 18/451,182, filed on Aug. 17, 2023, granted, now 12,033,693.
Application 18/451,182 is a continuation of application No. 18/159,123, filed on Jan. 25, 2023, granted, now 11,776,624, issued on Oct. 3, 2023.
Application 18/159,123 is a continuation of application No. 17/647,229, filed on Jan. 6, 2022, granted, now 11,594,278, issued on Feb. 28, 2023.
Application 17/647,229 is a continuation of application No. 17/018,684, filed on Sep. 11, 2020, granted, now 11,257,541, issued on Feb. 22, 2022.
Claims priority of application No. 2019-170378 (JP), filed on Sep. 19, 2019.
Prior Publication US 2024/0321348 A1, Sep. 26, 2024
Int. Cl. G11C 16/08 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G06F 12/02 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G06F 12/0246 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory device including a first plurality of memory cells capable of storing n bits of data and a second plurality of memory cells capable of storing n bits of data (where n is a natural number equal to or greater than 2); and
a memory controller is configured to control the semiconductor memory device, wherein
the semiconductor memory device is configured to read data of the first plurality of memory cells and data of the second plurality of memory cells in response to a request from the memory controller, the request for reading the data of the first plurality of memory cells and the data of the second plurality of memory cells,
part of a read operation of the data of the first plurality of memory cells and part of a read operation of the data of the second plurality of memory cells are executed in parallel
the memory controller is configured to write first data into an i-th bit of the n bits of the first plurality of memory cells and second data into a j-th bit of the n bits of the second plurality of memory cells when the first data and the second data are written into the semiconductor memory device, the j-th bit differing from the i-th bit,
a logical address of the first data is smaller than a logical address of the second data, and
the logical address of the first data and the logical address of the second data are consecutive.