US 12,300,312 B2
Pre-charging bit lines through charge-sharing
Mahmut Sinangil, Campbell, CA (US); Chiting Cheng, Taichung (TW); Hung-Jen Liao, Hsinchu (TW); and Tsung-Yung Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Nov. 10, 2023, as Appl. No. 18/506,213.
Application 16/517,929 is a division of application No. 15/896,247, filed on Feb. 14, 2018, granted, now 10,410,715, issued on Sep. 10, 2019.
Application 18/506,213 is a continuation of application No. 17/010,901, filed on Sep. 3, 2020, granted, now 11,848,047.
Application 17/010,901 is a continuation of application No. 16/517,929, filed on Jul. 22, 2019, granted, now 10,847,217, issued on Nov. 24, 2020.
Application 15/896,247 is a continuation of application No. 15/231,293, filed on Aug. 8, 2016, granted, now 9,922,701, issued on Mar. 20, 2018.
Prior Publication US 2024/0079053 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/419 (2006.01); G11C 7/12 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 7/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a bit line and a complementary bit line coupled to a memory cell;
a voltage supply line coupled to the memory cell; and
a circuit configured to charge the bit line by:
charging the voltage supply line to a first voltage level while the voltage supply line is electrically isolated from the bit line; and
transferring a charge from the voltage supply line to the bit line while the voltage supply line is electrically isolated from a voltage source and the complementary bit line.