US 12,299,940 B2
Interleaving of variable bitrate streams for GPU implementations
Sreenivas Kothandaraman, Sammamish, WA (US); Stephen Junkins, Bend, OR (US); Srihari Pratapa, Seattle, WA (US); and Prasoonkumar Surti, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,310.
Claims priority of provisional application 63/235,076, filed on Aug. 19, 2021.
Prior Publication US 2023/0057492 A1, Feb. 23, 2023
Int. Cl. G06T 9/00 (2006.01); G06T 1/20 (2006.01)
CPC G06T 9/001 (2013.01) [G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more processors including a graphic processor, the graphics processor including:
a super-compression encoder pipeline to perform variable width interleaved coding of one or more bitstreams to generate a contiguous bitstream, and
a super-compression decoder pipeline to decode the contiguous bitstream to regenerate the one or more bitstreams; and
memory for storage of data including data for graphics processing;
wherein the encoder pipeline is to:
perform parallel dictionary encoding on a bitstream of symbols by a workgroup of a plurality of workgroups, the workgroup to employ a plurality of encoders of the encoder pipeline to generate a plurality of token-streams of variable lengths;
create a histogram including at least tokens from the plurality of token-streams for the workgroup to generate an optimized entropy code for the plurality of token-streams;
utilize the optimized entropy code to entropy code each of the plurality of token-streams for the workgroup into an encoded bitstream; and
variably interleave the encoded bitstreams to generate an interleaved bitstream and record a size of the interleaved bitstream.