| CPC G06T 3/4007 (2013.01) [G06T 9/00 (2013.01); G06T 15/04 (2013.01)] | 20 Claims |

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1. A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 for generating an interpolated result P, the values E0 and E1 being formed from colour endpoint values C0 and C1 respectively, the circuit being configured to:
perform an interpolation between the colour endpoint values C0 and C1 to generate a first intermediate interpolated result C2;
determine whether the colour endpoint values C0 and C1 are low-dynamic range (LDR) values or high dynamic range (HDR) values;
in response to determining that the colour endpoint values are LDR values, determine the interpolated result P such that the interpolated result P satisfies the equation
P=└((C2<<8)+C2+32)/64┘; (1)
or satisfies the equation
P=└((C2<<8)+128·64 +32)/64┘; (2)
and
in response to determining that the colour endpoint values are HDR values, determine the interpolated result P such that the interpolated result P satisfies the equation:
P=└(C2+2)>>2. (3)
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