US 12,299,766 B2
Providing native support for generic pointers in a graphics processing unit
Joydeep Ray, Folsom, CA (US); Prathamesh Raghunath Shinde, Folsom, CA (US); Ben J. Ashbaugh, Folsom, CA (US); Wei-Yu Chen, San Jose, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); Dmitry Yurievich Babokin, San Jose, CA (US); and Ankur N. Shah, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,066.
Prior Publication US 2023/0102538 A1, Mar. 30, 2023
Int. Cl. G06T 1/20 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06T 1/60 (2006.01)
CPC G06T 1/20 (2013.01) [G06F 9/30043 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06T 1/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processing unit (GPU) comprising:
a plurality of sub-cores each including a processing resource and a load/store pipeline;
the processing resource is operable to:
receive a memory access message including a memory type identifier and a pointer, wherein the memory type identifier is indicative of the pointer representing a generic pointer; and
output a load or store operation to the load/store pipeline based on the memory access message, including computing an address for the load or store operation by adding a base address of a named memory type of a plurality of named memory types referenced by the generic pointer to an offset into a memory of the named memory type; and
the load/store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.