| CPC G06F 8/433 (2013.01) | 9 Claims |
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1. A computer-implemented method of transforming a high-level program into configuration data executable by a coarse-grained reconfigurable (CGR) processor including one or more arrays of CGR units, comprising:
sectioning a dataflow graph of the high-level program into a plurality of sections to be mapped to the one or more arrays of CGR units of the CGR processor;
extracting performance information for each of the plurality of sections;
assigning a section of the plurality of sections that includes at least two computations dependent on a first data element to one or more CGR units of the CGR processor, wherein the first data element is loaded from a memory;
scheduling an additional load of the first data element from the memory based at least in part on the performance information for the section indicating available memory bandwidth for the section;
eliminating from the section, a buffer between a load of the first data element from the memory and one of the two computations dependent on the first data element;
generating the configuration data for the CGR processor including placed positions, data routing, and communication channels, wherein the configuration data, when loaded onto an instance of the one or more arrays of CGR units of the CGR processor, causes the one or more arrays of CGR units to implement at least the section of the dataflow graph; and
storing the configuration data in a non-transitory computer-readable storage medium.
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