US 12,299,413 B2
Dual vector arithmetic logic unit
Bin He, Orlando, FL (US); Brian Emberling, Santa Clara, CA (US); Mark Leather, Santa Clara, CA (US); and Michael Mantor, Orlando, FL (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Jan. 16, 2024, as Appl. No. 18/414,164.
Application 18/414,164 is a continuation of application No. 18/201,839, filed on May 25, 2023, abandoned.
Application 18/201,839 is a continuation of application No. 17/121,354, filed on Dec. 14, 2020, granted, now 11,675,568, issued on Jun. 13, 2023.
Prior Publication US 2024/0168719 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/57 (2006.01); G06F 9/38 (2018.01); G06F 17/16 (2006.01); G06T 1/20 (2006.01); G06F 15/80 (2006.01)
CPC G06F 7/57 (2013.01) [G06F 9/3851 (2013.01); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 17/16 (2013.01); G06T 1/20 (2013.01); G06F 15/8015 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a cache to store a set of operands transferred from a set of vector general purpose register (VGPR) banks; and
an execution unit comprising a first arithmetic logic unit (ALU) pipeline and a second ALU pipeline to selectively execute either a single instruction at each of the first ALU pipeline and the second ALU pipeline using the first set of operands in an execution cycle or a pair of independent instructions at respective ALU pipelines of the first ALU pipeline and the second ALU pipeline using the first set of operands in the execution cycle.